1. Field of the Invention
The invention relates to a method for making contact with one or more electrical contact surfaces on a surface of a substrate, and a device having a substrate with a surface on which electrical contact surfaces are arranged.
2. Description of the Related Art
The most widely established technology for interconnecting power semiconductor chips and connecting them to conductor tracks is thick-wire bonding (see Harmann, G., “Wire Bonding in Microelectronics, Materials, Processes, Reliability and Yield”, Mc Graw Hill 1998). In this technique ultrasound energy is used to achieve a permanent connection between the Al wire, which has a typical diameter of several 100 μm, and the contact surface, which on the chip is an Al or Cu surface on the power module, via an intermetallic connection.
Other techniques have been published as alternatives to bonding, such as the ThinPak technique (see Temple, V., “SPCO's ThinPak Package, an Ideal Block for Power Modules and Power Hybrids”, IMAPS 99 Conference, Chicago 1999). In this technique, contact is made with the chip surface via solder applied over holes in a ceramic plate.
In MPIPPS (Metal Posts Interconnected Parallel Plate Structures, see Haque S., et al., “An innovative Technique for Packaging Power Electronic Building Blocks Using Metal Posts Interconnected Parallel Plate Structures”, IEEE Trans Adv. Pckag., Vol. 22, No. 2, May 1999), the contacts are made by soldered copper posts.
Another way of making contact is via solder bumps for flip-chip technology (Liu, X., et al., “Packaging of Integrated Power Electronics Modules Using Flip-Chip Technology”, Applied Power Electronics Conference and Exposition, APEC '2000). This method additionally enables improved heat dissipation because the power semiconductors can be soldered onto DCB substrates on the upper and lower face (DCB stands for Direct Copper Bonding) (see Gillot, C., et al., “A New Packaging Technique for Power Multichip Modules”, IEEE Industry Applications Conference IAS '99, 1999).
Making contact over a large area via vapor-deposited Cu leads is presented in (Lu, G.-Q., “3-D, Bond-Wireless Interconnection of Power Devices in Modules Will Cut Resistance, Parasitics and Noise”, PCIM May 2000, pp. 40-68), wherein the conducting-track insulation (Power Module Overlay Structure) is fabricated by vapor-phase deposition (CVD technique).
Using a patterned foil to make contact via an adhesive or solder process was published in (Krokoszinski, H.-J., Esrom, H., “Foil Clip for Power Module Interconnects”, Hybrid Circuits 34, September 1992).
U.S. Pat. No. 5,616,886 from Motorola proposes the bondless module without specifying any process details.